1. Field of the Invention
The present invention concerns apparatus for communication between a user system and a neural network of a perception system via a communication bus carrying information in the form of asynchronous pulses generated from analog signals produced by the neurones of the network.
2. Description of the Prior Art
An artificial perception system using a neural network is described in an article by Mortara et al. published in IEEE Journal of Solid State Circuits, Vol. 30, No. 6, June 1995.
FIGS. 1 and 2 of the accompanying drawings reproduce FIG. 1 of the above article.
The artificial neurones of a network 1 are associated with current/frequency converters 2 that allow for the activity of the neurones. The activity of a neurone is symbolized at 3a and can be represented by a time-varying analog magnitude (current or voltage), for example. The converter 2 converts this activity into a series of pulses 3b whose frequency is proportional to the amplitude of the analog magnitude. The outputs of the converters 2 are fed, via the encoder 4, to the communication bus 5, using a code specific to each neurone. FIG. 2 shows the activity of three neurones encoded on the five lines of the bus 5: the first and fourth wires for the first neurone (code 10010), the second and third wires for the second neurone (code 01100) and the fourth and fifth wires for the third neurone (code 00011).
The communication bus 5 terminates at a user circuit 6 at a greater or lesser distance from the network 1. This circuit includes a decoder 7 and activity accumulators 8, each accumulator restoring the activity signal of the associated neurone, as shown at 3c. 
The aforementioned article therefore describes a multiplexing method which differs from the usual multiplexing method in that it does not entail scanning all the neurones cyclically. To the contrary, when a pulse generated by the activity of a neurone must be transmitted, the neurone has asynchronous direct access to the bus by sending its network address on the bus. Consequently, the average number of pulses sent by a neurone is proportional to its activity. This multiplexing method has the advantage that the most active neurones can use the greater part of the bandwidth of the bus, which makes the system respond faster.
Clearly under the above conditions, and depending on the excitation of the network (for example by light if the network is optically sensitive), two or more neurones can access the bus simultaneously. This is shown in the righthand part of FIG. 2 in which pulses specific to neurones with respective row codes 10010 and 00011 coincide in time at a moment shown by the chain-dotted line C.
Thus, unless particular precautions are taken, if all the neurones have unrestricted access to the bus, there is an attendant risk of xe2x80x9ccollisionsxe2x80x9d. Of course, careful choice of the neurone address codes prevents addressing errors, but this restricts the number of codes available and does not prevent collisions, the probability of which increases with the increasing total activity of the neurones and the width of the pulses.
From the point of view of network performance, collisions cause unwanted attenuation of the transmitted signal and uncertainty in the received signal (noise).
To avoid these problems and to improve the performance of the communication device a system is required for arbitrating access to the transmission bus.
This arbitration system can be that described in an article by J. Lazzaro et al. xe2x80x9cSilicon auditory processors as computer peripheralsxe2x80x9d, published in IEEE Transactions on Neural Networks, vol. 4 pages 523 to 528, May 1993. In this case, when a neurone wishes to send a pulse, it submits a request to the arbitration system which verifies if the communication bus is free and returns an authorization to send signal to the neurone. If two neurones wish to access the bus at the same time, the arbitration system uses an arbitration tree to choose one of the two neurones and has the other one wait. Although this can prevent collisions, it does so at the cost of significant complexity of the circuits. Request and authorization conductors must be provided for each row and each column of the array, together with an arbitration tree for the rows and the columns, which increases the complexity of the circuit. Also, the transmission speed is considerably reduced.
An aim of the invention is to provide apparatus for communication between a neural network and a user system via an information transmission bus that does not complicate the units upstream and downstream of the bus and which, through improved arbitration, achieves faster transmission for comparable quality than can be obtained with a system operating without arbitration.
The invention therefore consists in apparatus for communication via a transmission bus between a user system and a neural network made up of neurones connected in an addressable matrix, the apparatus including an activity/frequency converter for each neurone adapted to provide at its outputs pulses whose frequency represents the activity of the neurone, the outputs of the converters associated with the neurones of the matrix being connected to an encoder by which the pulses are allocated a binary code specific to the neurone that caused them to be produced and the encoder being connected to the bus for transmitting the codes to the user system, the device also including arbitration means for determining the order of succession on the transmission bus of the various codes produced by the neurones of the network, the arbitration means comprising, for each of the converters, a circuit for controlling inhibition of operation of its associated converter and blocking means connected in common to all the converters to transmit to them a temporary blocking command, each inhibition control circuit being adapted to detect the presence of a pulse at the output of its associated converter and, while any such pulse is present, to activate the blocking means so that they transmit to the other converters the command temporarily blocking their operation.
By virtue of the above features, the invention exploits for the purposes of arbitration the presence of a pulse at the output of the converter corresponding to the neurone active at the time concerned to block the operation of all the other converters, for as long as the pulse produced by that neurone lasts. This leads to a very simple circuit requiring only a minimum of simple components, although the arbitration is totally reliable.
Also, the bandwidth of the communication bus is significantly increased.
Advantageously, for maximum simplification of the means employed, the blocking means comprise a reference voltage source connected to a voltage divider having an intermediate node connected to each of the control circuits and to a blocking input of each converter, each control circuit is adapted to modify the potential of the intermediate node while a pulse is present at the output of the associated converter, the modification of the potential, by activating the blocking inputs of all the other converters, preventing the production of any pulse thereby.
According to another advantageous feature of the invention, the voltage divider comprises the series-connected combination of a resistor and a capacitor the common point of which forms the intermediate node and the series-connected circuit is connected between the reference voltage source and ground.
If, as is known per se, each converter comprises a Schmitt trigger to whose input the activity signal from the neurone connected to that converter is applied and whose output is connected to the encoder, the trigger is connected to two hysteresis voltage sources between which hysteresis voltages the activity signal must evolve to cause the trigger to change state and thereby determine the length and the spacing of the pulses, and one of the hysteresis voltage sources is the intermediate node of the voltage divider.
In a first variant of the invention, each inhibition control circuit comprises a transistor whose gate is connected to the output of the associated converter and whose source-drain path is connected between a current source and the intermediate node.
In a second variant of the invention, each inhibition control circuit comprises a transistor whose gate is connected to the output of the associated converter and whose source-drain path is connected between the intermediate node of the divider and ground.
In a third variant of the invention, each inhibition control circuit comprises a capacitor connected between the output of the converter and the intermediate node and a diode connected between the reference voltage source and the intermediate node of the divider.
Other features and advantages of the invention will become apparent during the course of the following description which is given by way of example only and with reference to the accompanying drawings.